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| the mark h shows major revised points. description the m pd75512(a) is a 4-bit single-chip microcomputer which employs 75x series architecture, and its performance is comparable to that of an 8-bit microcomputer. in addition to its high-speed processing capabilities, the m pd75512(a) is also capable of processing data in units of 1, 4, or in 8-bits. with its internally provided a/d converter and serial interface, the m pd75512(a) provides the highest performance in its class. detailed functions are described in the following users manual. be sure to read it for designing. m pd75516 users maual: iem-5049 features ? higher reliability than m pd75512 ? adequate i/o lines: 64 (can be provided with pull-up/pull-down resistors: 47) ? built-in 8-bit serial interface: 2-ch nec standard serial bus interface (sbi) internally provided ? built-in 8-bit a/d converter: 8-ch ? variable instruction execution time function which is convenient for high-speed operation and power saving 0.95 m s/1.95 m s/15.3 m s (at 4.19 mhz operation), 122 m s (at 32.768 khz operation) ? program memory (rom) size: 12,160 8 bits ? data memory (ram) size: 512 4 bits ? high-performance timer function: 4-ch 8-bit timer/event counter watch timer 8-bit basic interval timer timer/pulse generator: capable of outputting 14-bit pwm ? clock operation for reduced power consumption possible (5 m a typ. at 3 v operation) ? prom version ( m pd75p516) available applications switable for automotive and transportation equipments, etc. ? nec corporation 1991 document no. ic-2815a (o. d. no. ic-8265a) date published january 1994 p printed in japan data sheet mos integrated circuit m pd75512(a) the information in this document is subject to change without notice. 4-bit single-chip microcomputer
m pd75512(a) 2 electrical specifications item product ordering information part number package quality grade m pd75512gf(a)-xxx-3b9 80-pin plastic qfp special (14 20mm) remarks: xxx is rom code number. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. difference between m pd75512(a) and m pd75512 m pd75512(a) m pd75512 quality grade special standard absolute maximum ratings differ in high-level and low-level output current dc characteristics differ in low-level output voltage a/d converter characteristics differ in ambient temperature range and absolute accuracy m pd75512(a) 3 m pd75512(a) functions item function internal rom 12160 8 bits memory size ram 512 4 bits genearl-purpose register (4 bits 8 or 8 bits 4) 4 banks instruction cycle ? 0.95 m s/1.91 m s/15.3 m s (main system clock: at 4.19 mhz) ? 122 m s (subsystem clock: at 32.768 khz) total 64 lines cmos inputs 16 lines (also serve as int, sio, ppo, analog input; can be pulled up by software: 7 lines) input/ output cmos 28 lines ports input/outputs ? can be pulled up by software: 16 lines ? can be pulled down by mask option: 4 lines n-ch open-drain 20 lines (10 v withstand voltage; pins that can be pulled up by mask option: 20) input/outputs a/d converter 8-bit resolution 8 channels (successive approxmation type) ? operation voltage: v dd = 3.5 to 6.0 v ? timer/event counter ? basic interval timer ? timer/pulse generator (capable of outputting 14-bit pwm) ? watch timer ? nec standard serial bus interface (sbi)/3-line sio: 1 channel ? normal clock synchronized serial interface (3-line sio): 1 channel vector interrupt external: 3, internal: 4 test input external: 1, internal: 1 ? bit data set/reset/test/boolean operation instruction instruction set ? 4-bit data transfer/operation/increment/decrement /compare instructions ? 8-bit data transfer/operation/increment/decrement /compare instructions ? ceramic/crystal oscillator for main system clock: 4.19 mhz ? crystal oscillator for subsystem clock: 32.768 khz operation voltage v dd = 2.7 v to 6.0 v package 80-pin plastic qfp (14 20mm) system clock generator ? ? timer/counter 4 channels serial interface 2 channels h m pd75512(a) 4 contents 1. pin configuration ..................................................................................................................... 6 2. internal block diagram ......................................................................................................... 7 3. pin functions .............................................................................................................................. 8 3.1 port pins ............................................................................................................................................. 8 3.2 non-port pins ................................................................................................................................... 10 3.3 pin input/output circuits ............................................................................................................ 11 3.4 recommended conditions for unused pins .......................................................................... 14 3.5 mask option selection ................................................................................................................. 15 4. memory configuration .......................................................................................................... 16 5. peripheral hardware functions ........................................................................................ 19 5.1 port ...................................................................................................................................................... 19 5.2 clock generator circuit ............................................................................................................. 20 5.3 clock output circuit ..................................................................................................................... 21 5.4 basic interval timer ...................................................................................................................... 22 5.5 watch timer ...................................................................................................................................... 23 5.6 timer/event counter ..................................................................................................................... 23 5.7 timer/pulse generator ................................................................................................................. 25 5.8 serial interface ............................................................................................................................... 26 5.9 a/d converter ................................................................................................................................... 30 5.10 bit sequential buffer ................................................................................................................... 31 6. interrupt functions ................................................................................................................ 31 7. standby functions ................................................................................................................... 33 8. reset functions ......................................................................................................................... 34 9. instruction set .......................................................................................................................... 36 10. electrical specifications ....................................................................................................... 44 11. package drawings .................................................................................................................... 57 12. recommended soldering conditions ................................................................................ 58 m pd75512(a) 5 appendix a. functional differences among m pd755xx(a) series products ............. 59 appendix b. development tools ................................................................................................ 60 appendix c. related documents ................................................................................................ 61 m pd75512(a) 6 1. pin configuration ic: internally connected (connect directly to v ss ) *: power must be supplied to both v dd pins. an0 pd75512gf(a) ?b9 m an4/p150 p120 av ss an1 1 80 21 22 23 24 25 26 p93 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 64 27 28 29 30 31 32 33 34 35 36 37 38 39 40 an2 an3 an5/p151 an6/p152 an7/p153 p121 p122 p123 p130 p131 p132 p133 av ref v dd v dd * p113 p112 p111 p110 p103 p102 p101 p100 p92 p91 p90 si1/p83 so1/p82 sck1/p81 ppo/p80 kr7/p73 kr6/p72 kr5/p71 kr4/p70 kr3/p63 kr2/p62 kr1/p61 kr0/p60 p53 p52 p51 p50 v ss p43 p42 p41 p40 p33 p32 p31 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p140 p141 p142 p143 reset x2 x1 ic xt2 xt1 v ss p00/int4 p01/sck0 p02/so0/sb0 p03/si0/sb1 p10/int0 p11/int1 p12/int2 p13/ti0 p20/pto0 p21 p22/pcl p23/buz p30 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 m pd75512(a) 7 2. internal block diagram port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port10 port11 port12 port13 port14 port15 4 4 p10-p13 p00-p03 4 p20-p23 4 4 p30-p33 4 p40-p43* 4 p50-p53* 4 p60-p63 4 p70-p73 p80-p83 4 p90-p93 4 p100-p103 4 p110-p113 4 p120-p123* 4 p130-p133* 4 p140-p143* p150-p153 4 sp (8) bank general reg. cy alu program counter (14) rom program memory 12160 8 bits decode and control ram data memory 512 x 4 bits ti0/p13 timer/event counter #0 intt0 pto0/p20 buz/p23 watch timer intw intcsi serial interface0 si0/sb1/p03 so0/sb0/p02 sck0/p01 int0/p10 int1/p11 int2/p12 int4/p00 kr0/p60 kr7/p73 8 interrupt control bit seq. buffer (16) basic interval timer intbt ppo/p80 timer/pulse generator inttpg serial interface1 si1/p83 so1/p82 sck1/p81 a/d converter av ref av ss an0-an3 an4 /p150-an7/p15 f /2 x n v dd v ss reset pcl/p22 xt1 xt2 x1 x2 sub main clock output control clock divider clock generator stand by control cpu clock 4 f *: ports 4, 5, and 12 to 14 are 10 v middle voltage, n-ch open-drain input/output ports. m pd75512(a) 8 3. pin functions 3.1 port pins (1/2) input/ pin input/ shared function 8-bit when reset output name output pin i/o circuit type* p00 int4 4-bit input port (port0). b for p01 to p03, built-in pull-up p01 sck0 resistors can be specified in 3-bit f -a input units by software. x input p02 so0/sb0 f -b p03 si0/sb1 m -c p10 int0 with noise elimination function p11 int1 input 4-bit input port (port1). x input b -c p12 int2 built-in pull-up resistors can be specified by software in 4-bit units. p13 ti0 p20 pto0 4-bit input/output port (port2). p21 input/ built-in pull-up resistors can be output specified by software in 4-bit units. x input e-b p22 pcl p23 buz p30 programmable 4-bit input/output port (port3). p31 input/ input/output can be specified in output bit units. x input e-c p32 built-in pull-up resistors can be specified by software in 4-bit unit. p33 n-ch open-drain 4-bit input/output high level port (port4). (when pull-up p40 to input/ a pull-up resistor can be provided resistor is m p43 output in bit units (mask option). provided) or 10v withstanding voltage in the high impedance open-drain mode. o n-ch open-drain 4-bit input/output high level port (port5). (when pull-up p50 to input/ a pull-up resistor can be provided resistor is m p53 output in bit units (mask option). provided) or 10v withstanding voltage in the high impedance open-drain mode. p60 kr0 programmable 4-bit input/ output port (port6). p61 input/ kr1 input/output can be specified in output bit units. o input f -c p62 kr2 built-in pull-up resistors can be specified by software in 4-bit units. p63 kr3 *: the number enclosed with a circle indicates schmitt trigger input. m pd75512(a) 9 3.1 port pins (2/2) input/ pin input/ shared function 8-bit when reset output name output pin i/o circuit type* p70 kr4 4-bit input/output port (port7). p71 input/ kr5 built-in pull-up resistor can be output specified in 4-bit units by software. o input f -a p72 kr6 p73 kr7 p80 ppo e p81 sck1 f input 4-bit input port (port8). x input p82 so1 e p83 si1 b low level 4-bit input/output port (port9). (when pull- p90 to input/ built-in pull-up resistors can be x down resistor v p93 output specified in bit units by mask is provided) option. or high impedance p100 to input/ 4-bit input/output port (port10). input e p103 output x p110 to input/ 4-bit input/output port (port11). input e p113 output n-ch open-drain 4-bit input/output high level port (port12). (when pull-up p120 to input/ a pull-up resistor can be provided resistor is m p123 output in bit units (mask option). x provided) or 10v withstanding voltage in the high impedance open-drain mode. n-ch open-drain 4-bit input/output high level port (port13). (when pull-up p130 to input/ a pull-up resistor can be provided x resistor is m p133 output in bit units (mask option). provided) or 10v withstanding voltage in the high impedance open-drain mode. n-ch open-drain 4-bit input/output high level port (port14). (when pull-up p140 to input/ a pull-up resistor can be provided x resistor is m p143 output in bit units (mask option). provided) or 10v withstanding voltage in the high impedance open-drain mode. p150 to input an4 to an7 4-bit input port (port15). x input y-a p153 *: the number enclosed with a circle indicates schmitt trigger input. m pd75512(a) 10 3.2 non-port pins input/ pin input/ shared function when reset output name output pin circuit type* ti0 input p13 the external event pulse input for the timer/event b -c counter. pto0 output p20 timer/event counter output input e-b pcl output p22 clock output input e-b buz output p23 fixed frequency output (for buzzer output or input e-b system clock trimming) sck0 input/ p01 serial clock input/output input f -a output so0/sb0 input/ p02 serial data output input f -b output serial bus input/output si0/sb1 input/ p03 serial data input input m -c output serial bus input/output int4 input p00 edge detection vector interrupt input (both rising b edge and falling edge detection) int0 p10 edge detection vector synchronized interrupt input with clock input (detection edge selectable) b -c int1 p11 asynchronous int2 input p12 edge detection testable input asynchronous b -c (rising edge detection) kr0-kr3 input p60-p63 parallel falling edge detection testable input input f -c kr4-kr7 input p70-p73 parallel falling edge detection testable input input f -a sck1 input/ p81 serial clock input/output input f output so1 output p82 serial data output input e si1 input p83 serial data input input b an0-an3 y input a/d converter analog input an4-an7 p150-p153 y-a av ref input a/c converter reference voltage input z av ss a/d converter reference ground pins for connecting the crystal ceramic oscillator to the main system clock generator. when x1, x2 input inputting the external clock, input the external clock to pin x1, and the reverse phase of the external clock to pin x2. xt1 input pins for connecting the crystal oscillator to the subsystem clock generator. when the external clock is used, inputs the external clock to pin xt1. in this case, pin xt2 must be left open. reset input system reset input b ppo output p80 timer/pulse generator pulse output input e ic internally connected. connect directly to v ss . v dd positive power supply v ss gnd *: the number enclosed with a circle indicates schmidt trigger input. xt2 m pd75512(a) 11 3.3 pin input/output circuits the following shows a simplified input/output circuit diagram for each pin of the m pd75512(a). type a type d type b type e in v dd input buffer of cmos standard data output disable out p?h n?h push-pull output that can be set in a output high-impedance state (both p-ch and n-ch are off) in schmitt trigger input with hysteresis characteristics data output disable type d type a in/out this input/output circuit consists of d-type push-pull outputs and type a input buffers. p.u.r. enable v dd p.u.r. p?h type b? type e b in data output disable type d type a p.u.r. enable v dd p.u.r. p?h in/out schmitt trigger input with hysteresis characteristics v dd p.u.r. : pull-up resistor p.u.r. : pull-up resistor p?h n?h fig. 3-1 pin input/output circuits (1/3) m pd75512(a) 12 type e-c data output disable type d type a p.u.r. enable v dd p.u.r. p?h in/out type f-b data output disable p.u.r. enable v dd p.u.r. p?h n-ch p-ch output disable (p-ch) output disable (n-ch) v dd in/out type b type f type f-c data output disable type d type b p.u.r. enable v dd p.u.r. p?h in/out data output disable type d type b in/out this input/output circuit consists of d-type push-pull outputs and type b schmitt trigger inputs. type f-a type m data output disable v dd p.u.r. in/out n-ch middle-voltage input buffer (can withstand up to +10 v) data output disable type d type b p.u.r. enable v dd p.u.r. p?h in/out (can withstand up to +10 v) p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor (mask option) fig. 3-1 pin input/output circuits (2/3) m pd75512(a) 13 type m-c type y-a type v type z data output disable p.u.r. enable v dd p.u.r. in/out p?h n-ch n?h in p?h av ss v dd v dd av ss sampling c + input enable reference voltage (from a voltage tap of series resistor string) in instruction data output disable type d type a in/out av av ss reference voltage ref p.d.r (mask option) n?h in p?h av ss v dd v dd av ss sampling c + input enable reference voltage (from a voltage tap of series resistor string) p.u.r. : pull-up resistor p.d.r. : pull-down resistor type y fig. 3-1 pin input/output circuits (3/3) m pd75512(a) 14 3.4 recommended conditions for unused pins table 3-1 recommended conditions for unused pins pin recommended conditions p00/int4 connect to v ss p01/ sck0 p02/so0/sb0 connect to v ss or v dd p03/si1/sb1 p10/int0-p12/int2 connect to v ss p13/ti0 p20/pto0 p21 p22/pcl p23/buz input state: connect to v ss or v dd p30-p33 output state: open p40-p43 p50-p53 p60/kr0-p63/kr3 p70/kr4-p73/kr7 p80/ppo p81/ sck1 connect to v ss or v dd p82/so1 p83/si1 p90-p93 p100-p103 p110-p113 input state: connect to v ss or v dd p120-p123 output state: open p130-p133 p140-p143 p150/an4-p153/an7 connect to v ss an0-an3 xt1 connect to v ss or v dd xt2 open av ref connect to v ss av ss ic connect directly to v ss h m pd75512(a) 15 3.5 mask option selection the following mask options are provided with the pins. (1) pull-up/pull-down resistor selection table 3-2 pull-up/pull-down resistor selection pins mask option p40-p43 (1) with pull-up resistor (2) without pull-up resistor p50-p53 (can be specified in bit units) (can be specified in bit units) p120-p123 p130-p133 p140-p143 p90-p93 (1) with pull-down resistor (2) without pull-down resistor (can be specified in bit units) (can be specified in bit units) (2) feedback resistor selection for the subsystem clock oscillation table 3-3 feedback resistor selection pins mask option xt1, xt2 (1) with feedback resistor (2) without feedback resistor (when the subsystem clock (when the subsystem clock is used) is not used) note : the operation is not affected if the feedback resistor is selected when the subsystem clock is not used. however, the supply current i dd is increased. h m pd75512(a) 16 4. memory configuration program memory (rom) ... 12160 8 bits (0000h-2f7fh) ? 0000h, 0001h : vector table to which address from which program is started is written after reset ? 0002h-000dh : vector table to which address from which program is started is written after interrupt ? 0020h-007fh : table area referenced by geti instruction data memory ? data area .... 512 4 bits (000hC1ffh) ? peripheral hardware area .... 128 4 bits (f80hCfffh) h m pd75512(a) 17 76 mbe mbe mbe mbe mbe mbe internal reset start address (upper 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 6 bits) int0 start address (lower 8 bits) int1 start address (upper 6 bits) int1 start address (lower 8 bits) intcsio0 start address (upper 6 bits) intcsio0 start address (lower 8 bits) intt0 start address (upper 6 bits) intt0 start address (lower 8 bits) 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 007fh 0800h 0fffh 1000h 1fffh geti instruction reference table 0 callf !faddr instruction entry address address 2000h 2f7fh brcb !caddr instruction branch address brcb !caddr instruction branch address rbe rbe rbe rbe rbe rbe mbe inttpg start address (upper 6 bits) 000ch rbe inttpg start address (lower 8 bits) br !addr instruction branch address call !addr instruction subroutine entry address br $addr instruction relational branch address (?5 to ?, +2 to +16) branch destination address and subroutine entry address for geti instruction brcb !caddr instruction branch address remarks: in addition to the above, branching to an address, for which only the lower 8 bits of the pc are modified, is possible by the br pcde and br pcxa instructions. fig. 4-1 program memory map m pd75512(a) 18 data memory memory bank general purpose register area 000h 01fh 008h (32 4) 256 4 stack area 100h 0ffh data area static ram (512 4) 1ffh 256 4 unmapped f80h 128 4 fffh peripheral hardware area 15 1 0 fig. 4-2 data memory map m pd75512(a) 19 5. peripheral hardware functions 5.1 port i/o ports are classified into following kinds: ? cmos input (ports 0, 1, 8, 15) : 16 ? cmos input/output (ports 2, 3, 6, 7, 9, 10, 11) : 28 ? n-ch open-drain input/output (ports 4, 5, 12, 13, 14) : 20 total : 64 table 5-1 port functions port function operation/feature remarks (pin name) also serves as the int4, sck0 , can be read or tested regardless of the operation so0/sb0, and si0/sb1 pins 4-bit input mode of the shared pin. also serves as int0 to 2, and tio pins can be specified for i/o in 4-bit units also serves as pto0, pcl and 4-bit i/o buz pins. can be specified for i/o in 1/4-bit units. 4-bit i/o whether or not the internal (n-ch can be specifiedfor pull-up resistor is provided open-drain, i/o in 4-bit units can be specified for each bit can sustain by mask option with 10v) can be specified for i/o in 1/4-bit units ports 6 and 7 can also serves as kr0-3. 4-bit i/o be paired to i/o can be specified data in 8-bit units i/o in 4-bit also serves as kr4-7. units 4-bit can be read or tested regardless of the operation also serves as ppo, sck1 , input mode of the shared pin. so1, and si1 pins. whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. port10 4-bit i/o can be specified for i/o in 4-bit units. port11 port12 4-bit i/o whether or not the internal (n-ch pull-up resistor is provided port13 open-drain, can be specified for i/o in 4-bit units. can be specified for each can sustain bit by mask option. port14 with 10v) port15 4-bit can be read or tested regardless of the operation also serves as an4-7 pins. input mode of the shared pins port9 4-bit i/o can be specified for i/o in 4-bit units. port8 port0 port1 port2 port4 port3 port5 port7 port6 ports 4 and 5 can be paired to i/o data in 8-bit units h m pd75512(a) 20 6.2 clock generator circuit the operation of the clock generator circuit is determined by the processor clock control regiser (ppc) and system clock control register (scc). this circuit can generate two types of clocks: main system clock and subsystem clock. in addition, it can also change the instruction execution time. 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz) 122 m s (subsystem clock: 32.768 khz) *: instruction execution. remarks 1: f x = main system clock frequency 2: f xt = subsystem clock frequency 3: f= cpu clock 4: pcc: processor clock control register 5: scc: system clock control register 6: one clock cycle (t cy ) of f is one machine cycle of an instruction. for t cy , refer to ac characteristics in 10. electrical specifications. fig. 5-1 clock generator block diagram v dd v dd xt1 xt2 x1 x2 f xt f x watch timer subsystem clock oscillator main system clock oscillator 1/2 1/16 1/8 to 1/4096 frequency divider ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?clock output circuit ?a/d converter ?int0 noise rejecter circuit internal bus wm.3 scc scc3 scc0 pcc pcc0 pcc1 pcc2 pcc3 halt* stop* 4 pcc2, pcc3 clear signal stop f/f qs r q s r halt f/f oscillator disable signal frequency divider 1/4 selector f ?cpu ?clock output circuit ?int0 noise rejecter circuit wait release signal from bt reset signal standby release signal from interrupt control circuit timer/pulse generator selector m pd75512(a) 21 5.3 clock output circuit the clock output circuit outputs clock pulse from the p22/pcl pin. this clock pulse is used for the remote control output, peripheral lsis, etc. ? clock output (pcl): f , 524 khz, 262 khz, 65.5 khz (operating at 4.19 mhz) fig. 5-2 clock output circuit configuration remarks: a measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken. selector output buffer pcl/p22 bit 2 of pmgb port2.2 port 2 input/ output mode specification bit p22 output latch internal bus clom3 clom2 clom1 clom0 clom 4 f f x /2 3 f x /2 4 f x /2 6 from the clock generator m pd75512(a) 22 5.4 basic interval timer the basic interval timer has these functions: interval timer operation which generates a reference time interrupt watchdog timer application which detects a program runaway selects the wait time for releasing the standby mode and counts the wait time reads out the count value from the clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx clear basic interval timer (8-bit frequency divider circuit) 3 4 8 bt clear set signal bt interrupt request flag irqbt wait release signal for standby release vector interrupt request signal internal bus btm3 btm2 btm1 btm0 btm set1* *: instruction execution fig. 5-3 basic interval timer configuration m pd75512(a) 23 5.5 watch timer the m pd75512(a) has a built-in 1-ch watch timer. the watch timer has these functions. sets the test flag (irqw) with 0.5 sec interval. the standby mode can be released by irqw. 0.5 second interval can be generated either from the main system clock or subsystem clock. time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. this is convenient for program debugging, test, etc. fixed frequency (2.048 khz) can be output to the p23/buz pin. this can be used for beep and system clock frequency trimming. the frequency divider circuit can be cleared so that zero second watch start is possible. wm70000wm2wm1wm0 selector frequency divider f w 2 7 (256 hz: 3.91 ms) intw (irqw set signal) f w 2 14 (2 hz 0.5 sec) selector f w (32.768 khz) f w 16 (2.048 khz) clear f x 128 (32.768 khz) f xt (32.768 khz) from the clock generator wm port2.3 bit 2 of pmgb output buffer p23/buz p23 output latch port 2 input/output mode bit test instruction 8 internal bus remarks: ( ) is for f x = 4.194304 mhz, f xt = 32.768 khz. fig. 5-4 watch timer block diagram 5.6 timer/event counter the m pd75512(a) has a built-in 1-ch timer/event counter. the timer/event counter has these functions: programmable interval timer operation outputs square-wave signal of an arbitrary frequency to the pto0 pin. event counter operation divides the ti0 pin input in n and outputs to the pto0 pin (frequency divider operation). supplies serial shift clock to the serial interface circuit. count condition read out function m pd75512(a) 24 internal bus 8 8 set1* tm07 tm06 tm05 tm04 tm03 tm02 tm01 tm00 tm0 port1.3 input buffer p13/ti0 from the clock generator mpx *: instruction execution timer operation start signal cp 8 8 modulo register (8) comparator (8) count register (8) clear t0 tmod0 reset toe0 port2.0 bit 2 of pgmb to serial interface p20/pto0 intt0 irqt0 set signal () reset irqt0 clear signal output buffer tout f/f to enable flag p20 output latch port 2 input/ output mode coinci- dence 8 fig. 5-5 timer/event counter block diagram m pd75512(a) 25 5.7 timer/pulse generator the m pd75512(a) contains a timer/pulse generator, that can be used as the timer or the pulse generator. timer/ pulse generator has the following functions. (a) function, when used in the timer mode ? 8-bit interval timer operation (irqtpg generation), for which the clock source can be changed in 5 steps. ? square waveform output to the ppo pin (b) function, when used in the pwm pulse generation mode ? 14-bit accuracy pwm pulse output to ppo pin (can be used as a d/a converter for electronics tuning). ? fixed time interval interrupt generation (2 15 /f x = 7.81ms: f x = 4.19 mhz) when no pulse output is required, the ppo pin can be used as 1-bit output port. note: when setting the stop mode, if the timer pulse generator is in operating mode, erroneous operation may occur. therefore, the timer/pulse generator must be set in no-operation state by the mode register, before setting the stop mode. internal bus 8 8 tpgm3 (set to 1 ) modh modulo register l (8) modulo register h (8) frequency divider f x 1/2 tpgm1 prescaler select latch (5) clear cp clear 8 count register (8) comparator (8) t f/f set coincidence modulo latch h (8) 8 tpgm4 tpgm5 tpgm7 ppo output buffer inttpg (irqtpg set signal) selector modl fig. 5-6 timer/pulse generator block diagram (timer mode) m pd75512(a) 26 internal bus modulo register h (8) modl modh modulo register l (8) tpgm3 tpgm1 f x 1/2 frequency divider modh(8) modl (6) 7-2 modulo latch (14) pwm pulse generator irqtpg set signal ( = 7.8 ms: f at 4.19mhz) x 2 15 f x inttpg tpgm5 tpgm7 selector output buffer ppo fig. 5-7 timer/pulse generator block diagram (pwm pulse generation mode) 5.8 serial interface the m pd75512(a) is provided with two serial interface channels. table 5-2 indicates differences between channel 0 and channel 1. table 5-2 differences between channel 0 and channel 1 serial transfer mode, funciton channel 0 channel 1 clock selection f x /2 4 , f x /2 3 , tout f/f, external clock f x /2 4 , f x /2 3 external clock 3-line transfer method msb first/lsb first selectable msb first serial i/o transfer completion serial transfer completion interrupt serial transfer completion flag (eot) flag request flag (irqcsi0) 2-line serial i/o usable unprovided serial bus interface (sbi) (1) serial interface function (channel 0) the m pd75512(a) is equipped with the following four modes: ? operation stop mode ? three-line serial i/o mode ? two-line serial i/o mode ? sbi mode (serial bus interface mode) m pd75512(a) 27 internal bus 8/4 8 88 p03/si/sb1 p02/so/sb0 p01/sck0 p01 output latch selector selector bit test slave address register (sva) address comparator shift register (sio0) set clr bit manipulation (8) (8) coincidence signal sbic relt cmdt so0 latch bit test ackt acke bsye busy/ acknowledge output circuit bus release/ command/ acknowledge detector circuit reld cmdd ackd serial clock counter serial clock control circuit intcsi0 control circuit mpx i ntcsi0 irqcsi0 set signal ( ) dq f x /2 3 f x /2 4 f x /2 6 tout f/f (from timer/ event counter) external sck0 (8) fig. 5-8 serial interface (channel 0) block diagram csim0 m pd75512(a) 28 (2) serial interface (channel 1) configuration m pd75512(a) serial interface (channel 1) has following two modes. ? operation stop mode ? 3-line serial i/o mode m pd75512(a) 29 fig. 5-9 serial interface (channel 1) block diagram bit manipulation 0 csim1 clear set serial transfer completion flag (eot) f /2 x 3 f /2 x 4 mpx 8 bit manipulation bit 7 serial operation mode (8) register 1 (8) internal bus 8 sio1 write signal (serial start signal) sio1 7 bit 0 shift register 1 (8) p83/si1 p82/so1 p81/sck1 serial clock counter (3) overflow clear q r s m pd75512(a) 30 5.9 a/d converter the m pd75512(a) is provided with an 8-bit resolution analog-to-digital (a/d) converter with eight channels of analog inputs (an0-an7). this a/d converter is of a successive approximation type. an0 an1 an2 an3 an4 an5 av ref av ss multiplexer sample hold circuit + tap decoder r/2 r/2 rr r 8 8 sa register (8) control circuit internal bus 0 adm6 adm5 adm4 soc eoc adm1 0 adm comparator 8 an6 an7 fig. 5-10 block diagram of a/d converter m pd75512(a) 31 address bit symbol l register 32103210 32103210 l = f l = c l = b l = 8 l = 7 l = 4 l = 3 l = 0 bsb3 bsb2 bsb1 bsb0 decs l incs l fc3h fc2h fc1h fc0h 5.10 bit sequential buffer ..... 16 bits the bit sequential buffer is a data memory specifically provided for bit manipulation. with this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. therefore, this buffer is very useful for processing long data in bit units. remarks: for the pmem.@l addressing, the specification bit is shifted according to the l register. fig. 5-11 bit sequential buffer format 6. interrupt functions the m pd75512(a) has 7 different interrupt sources and multiplexed interrupt with priority order. in addition to that, the m pd75512 is also provided with two types of test sources, of which int2 has two types of edge detection testable inputs. the interrupt control circuit of the m pd75512(a) has these functions: hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (iexxx) and interrupt master enable flag (ime). the interrupt start address can be arbitrarily set. interrupt request flag (irqxxx) test function (an interrupt generation can be confirmed by means of software). standby mode release (interrupts to be released can be selected by the interrupt enable flag). m pd75512(a) 32 internal bus 222 im2 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 int2 /p12 kr0/p60 kr7/p73 noise elimination circuit int bt intcsi0 intt0 inttpg selector both edge detection circuit edge detection circuit edge detection circuit rising edge detection circuit falling edge detection circuit irq4 irq0 irq1 irqcsi0 irqt0 irqtpg im2 interrupt enable flag (iexxx) (ime) vrqn decoder ist priority control circuit vector table address generator standby release signal fig. 6-1 interrupt control block diagram irq2 intw irqw 4 2 ips m pd75512(a) 33 can operate only when the external sck0 input is selected as the serial clock instruction for setting stop instrtuction halt instruction can be set only when operating on the main system clock can be set when operating either on the main system clock or the subsys- tem clock item mode stop mode halt mode clock oscillator only the main system clock can stop its operation. only the cpu clock f stops its operation. (oscillation continues) basic interval timer does not operate operates (sets irqbt with the reference time interval) system clock at the time of setting serial interface (channel 0) operates when the timer system clock is operating or external sck0 is selected serial interface (channel 1) can operate only when the external sck1 input is selected as the serial clock operates only when the main system clock is operating timer/event counter can only operate when the ti0 pin input is selected as system clock operates only when the main system clock is operating clock timer operates when f xt is selected as the count clock can operate a/d converter does not operate timer/pulse generator operates only when the main system clock is operating does not operate operates only when the main system clock is operating release signal cpu does not operate timer/pulse generator int1, int2, and int4 can operate, but int0 cannot operate an interrupt request signal from a piece of hardware, whose operation is enabled by the interrupt enable flag, or the reset signal input operation status 7. standby functions in order to fully exploit the m pd75512(a) low power dissipation, cpu operation can be stopped by setting the unit to the standby mode, thus, further reducing power dissipation. the m pd75512(a) features two standby modes, a stop mode and a halt mode. table 7-1 status in standby mode m pd75512(a) 34 8. reset functions when the reset signal is input, the m pd75512(a) is reset and each hardware is initialized as indicated in table 8-1. fig. 8-1 shows the reset operation timing. reset input wait (31.3ms/4.19mhz) operation mode or standby mode halt mode operation mode internal reset operation fig. 8-1 reset operation by reset input table 8-1 status of each hardware after reset (1/2) hardware reset input in standby mode reset input during operation program counter (pc) the contents of the lower 6 bits of address 0000h of the program memory are set to pc13-8, and the contents of address 0001h are set to pc7-0. same as left psw carry flag (cy) retained undefined skip flag (sk0-2) 0 0 interrupt status flag (ist0, 1) 0 0 bank enable flag (mbe, rbe) the contents of bit 6 of address 0000h of the program memory are set to rbe and those of bit 7 are set to mbe. same as left stack pointer (sp) undefined undefined data memory (ram) retained * undefined general-purpose register (x, a, h, l, d, e, b, c) retained undefined bank selection register (mbs, rbs) 0, 0 0, 0 basic interval timer counter (bt) undefined undefined timer/event counter counter (t0) 0 0 modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 mode register (btm) 0 0 timer/pulse generator modulo register 0 mode register 0 mode register (wm) 0 watch timer 0 retained retained * : data of address 0f8h to 0fdh of the data memory becomes undefined when a reset signal is input. m pd75512(a) 35 shift register (sio0) retained undefined operation mode 0 0 register (csim0) sbi control register 0 0 (sbic) slave address register retained undefined (sva) p01/sck0 output 1 1 latch a/d converter mode regiseter (adm), 04h (eoc = 1) 04h (eoc = 1) eoc sa register 7fh 7fh clock processor clock control 0 0 generator, register (pcc) clock output system clock control 0 0 circuit register (scc) clock output mode 0 0 register (clom) serial shift register retained undefined interface (sio1) (channel 1) operation mode 0 0 register 1 (csim1) serial transfer end 0 0 flag (eot) interrupt interrupt request flag reset (0) reset (0) function (irqxxx) interrupt enable flag 0 0 (iexxx) interrupt master enable 0 0 flag (ime) int0, int1, int2 mode 0, 0, 0 0, 0, 0 registers (im0, 1, 2) digital port output buffer off off output latch clear (0) clear (0) input/output mode 0 0 register (pmga, b, c) pull-up resistor 0 0 specification register (poga) bit sequential buffer (bsb0-3) retained undefined hardware reset input during operation reset input in standby mode table 8-1 status of each hardware after reset (2/2) serial interface (channel 0) m pd75512(a) 36 9. instruction set (1) operand representation and description describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to ra75x assembler package user's manual - language (eeu-730)). with some instructions, only one operand should be selected from several operands. the uppercase characters, +, and C are keywords and must be described as is. describe an appropriate numeric value or label as immediate data. representation description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label* bit 2-bit immediate data or label fmem fb0h to fbfh,ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr 0000h to 2f7fh immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (where bit0 = 0) or label portn port0 to port15 iexxx iebt, iecsi0, iet0, ie0, ie1, ie2, ie4, iew, ietpg rbn rb0-rb3 mbn mb0, mb1, mb15 *: only even addresses can be described in mem when processing 8-bit data. m pd75512(a) 37 (2) legend of operation field a : a register; 4-bit accumulator b : b register; 4-bit accumulator c : c register; 4-bit accumulator d : d register; 4-bit accumulator e : e register; 4-bit accumulator h : h register; 4-bit accumulator l : l register; 4-bit accumulator x : x register; 4-bit accumulator xa : register pair (xa); 8-bit accumulator bc : register pair (bc); 8-bit accumulator de : register pair (de); 8-bit accumulator hl : register pair (hl); 8-bit accumulator xa' : expanded register pair (xa') bc' : expanded register pair (bc') de' : expanded register pair (de') hl' : expanded register pair (hl') pc : program counter sp : stack pointer cy : carry flag; or bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 15) ime : interrupt mask enable flag ips : interrupt priority selector register iexxx : interrupt enable flag rbs : memory bank selector register mbs : memory bank selector register pcc : processor clock control register . : delimiter of address and bit (xx) : contents addressed by xx xxh : hexadecimal data m pd75512(a) 38 (3) symbols in addressing area field *1 mb = mbe . mbs (mbs = 0, 1, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (00h-7fh) data memory mb = 15 (80h-ffh) addressing mbe = 1 : mb = mbs (mbs = 0, 1, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 addr = 0000h-2f7fh *7 addr = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 program *8 caddr = 0000h-0fffh (pc 13, 12 = 00b) or memory 1000h-1f7fh (pc 13, 12 = 01b) or addressing 2000h-2f7fh (pc 13, 12 = 10b) *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh remarks 1: mb indicates memory bank that can be accessed. 2: in *2, mb = 0 regardless of mbe and mbs. 3: in *4 and *5, mb = 15 regardless of mbe and mbs. 4: *6 to *10 indicate areas that can be addressed. (4) machine cycle field in this field, s indicates the number of machine cycles required when an instruction having a skip function skips. the value of s varies as follows: when no instruction is skipped s = 0 when 1-byte or 2-byte instruction is skipped s = 1 when 3-byte instruction (br ! addr or call ! addr) is skipped s = 2 note : the geti instruction is skipped in one machine cycle. one machine cycle equals to one cycle of the cpu clock f , (=t cy ), and can be changed in three steps depending on the setting of the processor clock control register (pcc). m pd75512(a) 39 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area transfer mov a, #n4 1 1 a ? n4 string effect a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 string effect a hl, #n8 2 2 hl ? n8 string effect b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l = 0 a, @hle 1 2+s a ? (hl), then l ? le1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a,mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg 2 2 a ? reg xa, rp' 2 2 xa ? rp' reg1, a 2 2 reg1 ? a rp'1, xa 2 2 rp'1 ? xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l = 0 a, @hle 1 2+s a ? (hl), then l ? le1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' table movt xa, @pcde 1 3 xa ? (pc 13-8 +de) rom reference xa, @pcxa 1 3 xa ? (pc 13-8 +xa) rom m pd75512(a) 40 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area mov1 cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem. 2 2 cy ? (h+mem 3-0 .bit) *1 bit fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 )) ? cy *5 @h+mem.bit, 2 2 (h+mem 3-0 .bit) ? cy *1 cy adds a,#n4 1 1+s a ? a+n4 carry xa,#n8 2 2+s xa ? xa+n8 carry a,@hl 1 1+s a ? a+(hl) *1 carry xa,rp 2 2+s xa ? xa+rp carry rp1,xa 2 2+s rp1 ? rp1+xa carry addc a,@hl 1 1 a,cy ? a+(hl)+cy *1 xa,rp 2 2 xa,cy ? xa+rp+cy rp1,xa 2 2 rp1,cy ? rp1+xa+cy subs a,@hl 1 1+s a ? a-(hl) *1 borrow xa,rp 2 2+s xa ? xa-rp borrow rp1,xa 2 2+s rp1 ? rp1-xa borrow subc a,@hl 1 1 a,cy ? a-(hl)-cy *1 xa,rp 2 2 xa,cy ? xa-rp-cy rp1,xa 2 2 rp1,cy ? rp1-xa-cy and a,#n4 2 2 a ? a n4 a,@hl 1 1 a ? a (hl) *1 xa,rp 2 2 xa ? xa-rp rp1,xa 2 2 rp1 ? rp1 xa or a,#n4 2 2 a ? a n4 a,@hl 1 1 a ? a (hl) *1 xa,rp 2 2 xa ? xa rp rp1,xa 2 2 rp1 ? rp1 xa xor a,#n4 2 2 a ? a n4 a,@hl 1 1 a ? a (hl) *1 xa,rp 2 2 xa ? xa rp rp1,xa 2 2 rp1 ? rp1 xa bit transfer arithme- tic opera- tion m pd75512(a) 41 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area rorc a 1 1 cy ? a 0 , a 3 ? cy, a n-1 ? a n not a 2 2 a ? a incre- incs reg 1 1+s reg ? reg+1 reg = 0 ment/ rp1 1 1+s rp1 ? rp1+1 rp1 = 00h decre- @hl 2 2+s (hl) ? (hl)+1 *1 (hl) = 0 ment mem 2 2+s (mem) ? (mem)+1 *3 (mem) = 0 decs reg 1 1+s reg ? reg-1 reg = fh rp 2 2+s rp ? rp-1 rp = ffh compari- ske reg,#n4 2 2+s skip if reg = n4 reg = n4 son @hl,#n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a,@hl 1 1+s skip if a = (hl) *1 a = (hl) xa,@hl 2 2+s skip if xa = (hl) *1 xa = (hl) a,reg 2 2+s skip if a = reg a = reg xa,rp 2 2+s skip if xa = rp xa = rp set1 cy 1 1 cy ? 1 clr1 cy 1 1 cy ? 0 skt cy 1 1+s skip if cy = 1 cy = 1 not1 cy 1 1 cy ? cy carry flag manipu- lation accumu- lator manipu- lation m pd75512(a) 42 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area memory/ set1 mem.bit 2 2 (mem.bit) ? 1*3 bit fmem.bit 2 2 (fmem.bit) ? 1 *4 manipu- pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 1*5 lation @h+mem.bit 2 2 (h + mem 3-0 .bit) ? 1*1 clr1 mem.bit 2 2 (mem.bit) ? 0 *3 fmem.bit 2 2 (fmem.bit) ? 0 *4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 0*5 @h+mem.bit 2 2 (h+mem 3-0 .bit) ? 0*1 skt mem.bit 2 2+s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7-2 +l 3-2 .bit (l 1-0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if (h + mem 3-0 .bit) = 1 *1 (@h+mem.bit) = 1 skf mem.bit 2 2+s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2+s skip if (pmem 7-2 +l 3-2 .bit (l 1-0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2+s skip if (h + mem 3-0 .bit) = 0 *1 (@h+mem.bit) = 0 sktclr fmem.bit 2 2+s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7-2 +l 3-2 .bit *5 (pmem.@l) = 1 (l 1-0 )) = 1 and clear @h+mem.bit 2 2+s skip if (h+mem 3-0 .bit) = 1 and clear *1 (@h+mem.bit) = 1 and1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 . bit(l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 or1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit (l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 xor1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit (l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 branch br addr ? ? pc 13-0 ? addr *6 (the most suitable instruction is selectable from among br !addr, brcb !caddr, and br $addr depending on the assembler.) !addr 3 3 pc 13-0 ? addr *6 $addr 1 2 pc 13-0 ? addr *7 brcb !caddr 2 2 pc 13-0 ? pc 13,12 +caddr 11-0 *8 br pcde 2 3 pc 13-0 ? pc 13-8 +de pcxa 2 3 pc 13-0 ? pc 13-8 +xa m pd75512(a) 43 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area call !addr 3 3 (sp-4)(sp-1)(sp-2) ? pc 11-0 *6 (sp-3) ? mbe, rbe, pc 13,12 pc 13-0 ? addr, sp ? sp-4 callf !faddr 2 2 (sp-4)(sp-1)(sp-2) ? pc 11-0 *9 (sp-3) ? mbe, rbe, pc 13,12 pc 13-0 ? 00, faddr, sp ? sp-4 ret 1 3 mbe, rbe, pc 13,12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+4 rets 1 3+s mbe, rbe, pc 13,12 ? (sp+1) undefined pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+4, then skip unconditionally reti 1 3 pc 13,12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 push rp 1 1 (sp-1)(sp-2) ? rp, sp ? sp-2 bs 2 2 (sp-1) ? mbs, (sp-2) ? rbs, sp ? sp-2 pop rp 1 1 rp ? (sp+1)(sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 inter- ei 2 2 ime (ips.3) ? 1 rupt iexxx 2 2 iexxx ? 1 control di 2 2 ime (ips.3) ? 0 iexxx 2 2 iexxx ? 0 i/o in * 1 a,portn 2 2 a ? port n (n = 0-15) xa,portn 2 2 xa ? port n+1 ,port n (n = 4, 6) out * 1 portn,a 2 2 port n ? a (n = 2-7, 9-14) portn,xa 2 2 port n+1 ,port n ? xa (n = 4, 6) cpu halt 2 2 set halt mode (pcc.2 ? 1) control stop 2 2 set stop mode (pcc.3 ? 1) nop 1 1 no operation special sel rbn 2 2 rbs ? n (n = 0-3) mbn 2 2 mbs ? n (n = 0, 1, 15) geti * 2 taddr 1 3 . where tbr instruction, *10 pc 13-0 ? (taddr) 4-0 +(taddr+1) . where tcall instruction, (sp-4)(sp-1)(sp-2) ? pc 11-0 (sp-3) ? mbe, rbe, pc 13,12 pc 13-0 ? (taddr) 5-0 +(taddr+1) sp ? sp-4 . except for tbr and tcall depends on instructions, referenced instruction execution of instruction (taddr)(taddr+1) *1: when executing the in/out instruction, mbe = 0, or mbe = 1, and mbs = 15. * 2: the tbr, and tcall instructions are the assembler pseudo-instructions for the table definition of geti instruction. subrou- tine/ stack control ......................................................... ............................. ......................................................... ............................. m pd75512(a) 44 10. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd -0.3 to +7.0 v v i1 other than ports 4, 5, 12-14 -0.3 to v dd +0.3 v input voltage v i2 ports 4, 5, 12-14 w/pull-up -0.3 to v dd +0.3 v resistor open drain -0.3 to +11 v output voltage v o -0.3 to v dd +0.3 v high-level output i oh * 1 pin peak -10 ma current rms -5 ma all pins peak -30 ma rms -15 ma low-level output i ol * 1 pin peak 10 ma current rms 5 ma total of ports 0, 2, 3, 4 peak 100 ma rms 60 ma total of ports 5-11 peak 100 ma rms 60 ma total of ports 12-14 peak 40 ma rms 25 ma operating temperature t opt -40 to +85 c storage temperature t stg -65 to +150 c *: rms = peak value x ? duty operating supply voltage parameter symbol conditions min. max. unit a/d converter supply voltage v dd 3.5 6.0 v ambient temperature t a -40 +85 c timer/pulse supply voltage v dd 4.5 6.0 v generator ambient temperatuare t a -40 +85 c other circuits supply voltage v dd 2.7 6.0 v ambient temperatuare t a -40 +85 c capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 15 pf output capacitance c o pins other than thosemeasured are at 0 v 15 pf input/output c io 15 pf capacitance m pd75512(a) 45 main system clock oscillator circuit characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) oscillator recommended item conditions min. typ. max. unit constants ceramic oscillation v dd = osccillation 1.0 5.0 * 3 mhz frequency(f x )* 1 voltage range oscillation stabiliza- after v dd came to tion time* 2 min. value of oscillation voltage 4ms range crystal oscillation 1.0 4.19 5.0 * 3 mhz frequency (f x )* 1 oscillation stabiliza- v dd = 4.5 to 6.0 v 10 ms tion time* 2 30 ms external clock x1 input frequency 1.0 5.0 * 3 mhz (f x )* 1 x1 input high-, low-level widths (t xh , t xl ) 100 500 ns subsystem clock oscillator circuit characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) oscillator recommended item conditions min. typ. max. unit constants crystal oscillation* 1 32 32.768 35 khz frequency (f xt ) oscillation stabiliza- v dd = 4.5 to 6.0 v 1.0 2 s tion time* 2 10 s external clock xt1 input frequency 32 100 khz (f xt )* 1 xt1 input high-, low-level widths 5 15 m s (t xth , t xtl ) *1: only to express the characteristics of the oscillator circuit. for instruction execution time, refer to ac characteristics. 2: time required for oscillation to stabilize after v dd reaches the minimum value of the oscillation voltage range or the stop mode has been released. 3: when the oscillation frequency is 4.19 mhz < fx 5.0 mhz, do not select pcc = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 m s, falling short of the rated minimum value of 0.95 m s. x1 x2 c1 c2 x1 x2 c1 c2 x1 x2 pd74hcu04 m xt1 xt2 r c3 c4 xt1 xt2 open h m pd75512(a) 46 note: when using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v ss . do not connect the ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. when using the subsystem clock, therefore, exercise utmost care in wiring the circuit. h m pd75512(a) 47 dc characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit high-level input v ih1 ports 2, 3, 9-11, p80, p82 0.7v dd v dd v voltage v ih2 ports 0, 1, 6, 7, 15, p81, p83, reset 0.8v dd v dd v v ih3 ports 4, 5, 12-14 w/pull-up resistor 0.7v dd v dd v open-drain 0.7v dd 10 v v ih4 x1, x2, xt1 v dd -0.5 v dd v low-level input v il1 ports 2-5, 9-14, p80, p82 0 0.3v dd v voltage v il2 ports 0, 1, 6, 7, 15, p81, p83, reset 0 0.2v dd v v il3 x1, x2, xt1 0 0.4 v high-level output v oh v dd = 4.5 to 6.0 v, i oh = -1 ma v dd -1.0 v voltage i oh = -100 m av dd -0.5 v low-level output v ol ports 3, 4, and 5 v dd = 4.5 to 6.0 v, 0.2 1.0 v voltage i ol = 5 ma v dd = 4.5 to 6.0 v, i ol = 1.6 ma 0.4 v i ol = 400 m a 0.5 v sb0, 1 open-drain pull-up 0.2v dd v resistor 3 1 k w high-level input i lih1 v i = v dd other than below 3 m a leakage current i lih2 x1, x2, xt1 20 m a i lih3 v i = 9 v ports 4, 5, 12-14 20 m a (open-drain) low-level input i lil1 v i = 0 v other than below -3 m a leakage current i lil2 x1, x2, xt1 -20 m a high-level output i loh1 v o = v dd other than below 3 m a leakage current i loh2 v o = 9 v ports 4, 5, 12-14 20 m a (open-drain) low-level output i lol v o = 0 v -3 m a leakage current internal pull-up resistor r u1 ports 0, 1, 2, 3, 6, 7 v dd = 5.0 v 10% 15 40 80 k w (except p00) v i = 0v v dd = 3.0 v 10% 30 300 k w r u2 ports 4, 5, 12-14 v dd = 5.0 v 10% 15 40 70 k w v o = v dd -2.0 v v dd = 3.0 v 10% 10 60 k w internal pull-down r d v o = 2 v port 9 20 70 140 k w resistor m pd75512(a) 48 parameter symbol conditions min. typ. max. unit supply current * 1 i dd1 4.19 mhz* 2 crystal ooperation v dd = 5 v 10%* 3 39ma oscillator mode v dd = 3 v 10%* 4 0.55 1.5 ma i dd2 c1 = c2 = 22pf halt mode v dd = 5 v 10% 600 1800 m a v dd = 3 v 10% 200 600 m a i dd3 32.768 khz* 5 crystal operation v dd = 3 v 10% 40 120 m a oscillator mode i dd4 halt mode v dd = 3 v 10% 5 15 m a i dd5 xt1 = 0 v v dd = 5 v 10% 0.5 20 m a stop mode v dd = 3 v 10% 0.3 10 m a t a = 25 c5 m a *1: currents for the built-in pull-up resistor are not included. 2: including when the subsystem clock is operated. 3: when operand in the high-speed mode with the processor clock control register (pcc) set to 0011. 4: when operated in the low-speed mode with the pcc set to 0000. 5: when operated with the subsystem clock by setting the system clock control register (scc) to 1001 to stop the main system clock operation. m pd75512(a) 49 ac characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) (1) basic operation parameter symbol conditions min. typ. max. unit t cy w/main system clock v dd = 4.5 to 6.0 v 0.95 64 m s 3.8 64 m s w/sub-system clock 114 122 125 m s ti0 input frequency f ti v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz ti0 input high-, t tih ,v dd = 4.5 to 6.0 v 0.48 m s low-level widths t til 1.8 m s interrupt input high-, t inth , int0 *2 m s low-level widths t intl int1, 2, 4 10 m s kr0-7 10 m s reset low-level width t rsl 10 m s *1: the cpu clock ( f ) cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (scc), and processor clock control register (pcc). the figure on the right is cycle time t cy vs. supply voltage v dd characteristics at the main system clock. 2: 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 0123 456 0.5 1 2 3 4 5 6 60 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (with main system clock) m 64 70 guaranteed operating range cpu clock cycle time* 1 (minimum instruction execution time = 1 machine cycle) m pd75512(a) 50 parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level t kl1 v dd = 4.5 to 6.0 v (t kcy1 /2)-50 ns widths t kh1 (t kcy1 /2) -150 ns si set-up time (vs. sck - )t sik1 150 ns si hold time (vs. sck - )t ksi1 400 ns sck ? so output t kso1 r l = 1 k w ,v dd = 4.5 to 6.0 v 250 ns delay time c l = 100 pf* 1000 ns *: r l and c l are load resistance and load capacitance of the so output line. parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high-, low-level t kl2 v dd = 4.5 to 6.0 v 400 ns widths t kh2 1600 ns si set-up time (vs. sck - )t sik2 100 ns si hold time (vs. sck - )t ksi2 400 ns sck ? so output t kso2 r l = 1 k w , c l = 100 pf* v dd = 4.5 to 6.0 v 300 ns delay time 1000 ns *: r l and c l are load resistance and load capacitance of the so output line. (2) serial transfer operation (a) two-line and three-line serial i/o modes (sck: internal clock output) (b) two-line and three-line serial i/o modes (sck: external clock input) m pd75512(a) 51 (c) sbi mode (sck: internal clock output (master)) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level t kl3 v dd = 4.5 to 6.0 v t kcy3 /2-50 ns widths t kh3 t kcy3 /2-150 ns sb0, 1 set-up time t sik3 150 ns (vs. sck - ) sb0, 1 hold time t ksi3 t kcy3 /2 ns (vs. sck - ) sck ? sb0, 1 output t kso3 v dd = 4.5 to 6.0 v 0 250 ns delay time 0 1000 ns sck -? sb0, 1 t ksb t kcy3 ns sb0,1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns (d) sbi mode (sck: external clock input (slave)) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high-, low-level t kl4 v dd = 4.5 to 6.0 v 400 ns widths t kh4 1600 ns sb0, 1 set-up time t sik4 100 ns (vs. sck - ) sb0, 1 hold time t ksi4 t kcy4 /2 ns (vs. sck - ) sck ? sb0, 1 output t kso4 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns delay time c l = 100 pf* 0 1000 ns sck -? sb0, 1 t ksb t kcy4 ns sb0,1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns *: r l and c l are load resistance and load capacitance of the so output line. m pd75512(a) 52 (3) a/d converter (t a = -40 to +85 c, v dd = 3.5 to 6.0 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit absolute accuracy* 1 2.5 v av ref v dd * 2 2.0 lsb conversion time* 3 t conv 168/f x m s sampling time* 4 t samp 44/f x m s analog input voltage v ian av ss av ref v analog input impedance r an 1000 m w av ref current ai ref 1.0 2.0 ma *1: absolute accuracy excluding quantization error ( 1 C 2 lsb) 2: set adm1 as follows, in respect to the reference voltage of the ad converter (av ref ). adm1 can be set to either 0 or 1 when 0.6v dd av ref 0.65v dd 3: time since execution of conversion start instruction until eoc = 1 (40.1 m s: f x = 4.19 mhz) 4: time since execution of conversion start instruction until end of sampling (10.5 m s: f x = 4.19 mhz) 2.5 v 0.6 v dd 0.65 v dd v dd (3.5 to 6.0 v) adm1=0 adm1=1 av ref m pd75512(a) 53 ac timing test point (excluding x1 and xt1 inputs) x1 input v dd ?.5v 0.4 v t xl t xh 1/f x xt1 input v dd ?.5v 0.4 v t xtl t xth 1/f xt ti0 t til t tih 1/f ti clock timing ti0 timing test points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd m pd75512(a) 54 serial transfer timing three-line serial i/o mode: sck t kl1 t kh1 t kcy1 output data t sik1 t ksi1 t kso1 input data si so two-line serial i/o mode: sck t kl2 t kh2 t kcy2 t sik2 t ksi2 t kso2 sb0,1 m pd75512(a) 55 serial transfer timing bus release signal transfer: sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0,1 t kh3,4 t sbk t sbh t sbl t ksb command signal transfer: sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0,1 t kh3,4 t sbk t ksb interrupt input timing int0, 1, 2, 4 kr0-7 t intl t inth reset input timing: reset t rsl m pd75512(a) 56 low-voltage data retention characteristics of data memory in stop mode (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply v dddr 2.0 6.0 v voltage data retention supply i dddr v dddr = 2.0 v 0.1 10 m a current* 1 release signal set time t srel 0 m s oscillation stabilization t wait released by reset 2 17 /f x ms wait time* 2 released by interrupt *3 ms *1: does not include current flowing through internal pull-up resistor 2: the oscillation stabilization wait time is the time during which the cpu is stopped to prevent unstable operation when oscillation is started. 3: depends on the setting of the basic interval timer mode register (btm) as follows: btm3 btm2 btm1 btm0 wait time ( ): f x = 4.19 mhz C0002 20 /f x (approx. 250 ms) C0112 17 /f x (approx. 31.3 ms) C1012 15 /f x (approx. 7.82 ms) C1112 13 /f x (approx. 1.95 ms) data retention timing (releasing stop mode by reset) data retention timing (standby release signal: releasing stop mode by interrupt) stop mode data retention mode stop instruction execution v dd reset v dddr t srel t wait operation mode internal reset operation halt mode stop mode data retention mode stop instruction execution v dd v dddr t srel t wait operation mode halt mode standby release signal (interrupt request) m pd75512(a) 57 11. package drawings n a m f b 64 65 40 k l 80 pin plastic qfp (14 20) 80 1 25 24 41 g d c p detail of lead end s q 55? m i h j p80gf-80-3b9-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.8 0.35 0.10 0.15 20.0 0.2 0.929 0.016 0.039 0.031 0.006 0.031 (t.p.) 0.795 note m n 0.15 0.15 1.8 0.2 0.8 (t.p.) 0.006 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.014 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 m pd75512(a) 58 12. recommended soldering conditions it is recommended that m pd75512(a) be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document "semiconductor devices mounting manual" (iei-616). for other soldering methods and conditions, consult nec. table 12-1 soldering conditions of surface mount type m pd75512gf(a)-xxx-3b9: 80-pin plastic qfp (14 20 mm) soldering method soldering conditions symbol for recommended condition infrared reflow package peak temperature: 230 c, ir30-00-1 time: 30 seconds max. (210 c min.), number of times: 1 vps package peak temperature: 215 c, vp15-00-1 time: 40 seconds max. (200 c min.), number of times: 1 wave soldering soldering bath temperature: 260 c max., ws60-00-1 time: 10 seconds max., number of times: 1, pre-heating temperature: 120 c max. (package surface temperature) pin partial heating pin temperature: 300 c max., time: 3 seconds max. (per side) caution: do not use two or more soldering methods in combination (except the pin partial heating method). a model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235 c, number of times: 2, and an extended number of days) is also available. for details, consult nec. notice m pd75512(a) 59 appendix a. functional differences among m pd755xx(a) series products m pd75512(a) m pd75516(a) m pd75p516 rom configuration mask rom eprom/one-time prom rom (bit) 12160 x 8 16256 x 8 16256 x 8 ram (bit) 512 x 4 mask option ? ports 4, 5, 12, 14 are provided with internal pull-up resistors. not provided ? port 9 is provided with an internal pull-down resistor. v pp , prom, pins for programming not provided provided led direct drive not offered offered supply voltage range 2.7 to 6.0 v 4.75 to 5.5 v absolute maximum differ in high-level / low-level output current ratings dc characteristics differ in low-level output voltage a/d converter differ in ambient temperature range and absolute accuracy characteristics quality grade special standard package 80-pin plastic qfp (14 x 20 mm) ? 80-pin plastic qfp (14 x 20 mm) ? 80-pin ceramic wqfn electrical specifi- cations product item m pd75512(a) 60 appendix b. development tools the following development support tools are readily available to support development of systems using m pd75512(a): hardware ie-75000-r * 1 in-circuit emulator for 75x series ie-75001-r ie-75000-r-em * 2 emulation board for ie-75000-r and ie-75001-r ep-75516gf-r emulation prove for m pd75512(a), provided with 80-pin conversion socket ev-9200g-80. pg-1500 prom programmer pa-75p516gf prom programmer adapter solely used for m pd75p516gf. it is connected to pg-1500. software ie control program pg-1500 controller ra75x relocatable assembler * 1: maintenance product 2: not provided with ie-75001-r. 3: ver.5.00/5.00a has a task swap function, but this function cannot be used with this software. remarks: for development tools from other companies, refer to 75x series selection guide (if-151). ev-9200g-80 host machine pc-9800 series (ms-dos tm ver.3.30 to ver.5.00a* 3 ) ibm pc/at tm (pc dos tm ver.3.1) m pd75512(a) 61 appendix c. related documents h m pd75512(a) 62 [memo] m pd75512(a) 63 static electricity (all mos devices) exercise care so that mos devices are not adversely influenced by static electricity while being handled. the insulation of the gates of the mos device may be destroyed by a strong static charge. therefore, when transporting or storing the mos device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case nec uses for packaging and shipment, and use grounding when assembling the mos device system. do not leave the mos device on a plastic plate and do not touch the pins of the device. handle boards on which mos devices are mounted similarly . processing of unused pins (cmos devices only) fix the input level of cmos devices. unlike bipolar or nmos devices, if a cmos device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. therefore, fix the input level of the device by using a pull-down or pull-up resistor. if there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to v dd or gnd through a resistor. refer to processing of unused pins in the documents of each devices. a status before initialization (all mos devices) the initial status of mos devices is undefined upon power application. since the characteristics of an mos device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. the output status of pins, i/o setting, and register contents upon power application are not guaranteed. however, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. when using a device with a reset function, be sure to reset the device after power application. general notes on cmos devices m pd75512(a) 64 no p art of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for the applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime system, etc. ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation. [memo] m4 92.6 |
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